A wide variety of memory devices can be used to maintain and store data and instructions for various computers and similar systems. Non-volatile memory (“NVM”) devices, e.g., EPROM, EEPROM, and flash memory, do not require power to retain information that is stored in them.
Conventional flash memories are constructed using either NAND or NOR architectures. The memory cells that make up these architectures can be formed into two-dimensional arrays, and typically include a metal oxide semiconductor transistor having a source, a drain, a channel in a substrate or P-well, a floating gate, and a control gate. Further, each memory cell is addressed by a respective bit line and word line. In conventional NOR flash architectures, the control gate of each memory cell is connected to a word line associated with a row of memory cells. In addition, the drain of each memory cell is connected to a bit line associated with a column of memory cells, and the source of each memory cell is connected to a common source node.
In conventional NAND flash architectures, although the control gate of each memory cell is connected to a word line associated with a row of memory cells, each memory cell associated with a bit line is connected in series with other memory cells associated with that bit line; one end of the bit line is connected to one of the memory cells of the series of memory cells, and the another memory cell of the series of memory cells is connected to a source line. Therefore, NAND flash memory cell read access time is slower than NOR flash memory cell read access time because unlike NOR flash memory cells, the drain of each of the NAND flash memory cells does not connect to a common bit line: NAND flash memory read parasitics are higher because of increased resistance in the read path of each bit, due to the series connection of memory cells associated with a particular word line.
Conventional NOR flash architectures are programmed and erased with techniques called “hot electron injection” and “hot hole injection.” Hot electron and hot hole injection require applying high current and an associated electric field across the control gate and source or drain region of memory cells. Therefore, typical NOR flash architectures require circuits that provide large program and erase currents, which limits the program and erase time of the memory cells of NOR flash architectures.
In conventional NAND flash architectures, memory cells are programmed and erased with a technique called “Fowler-Nordhiem tunneling” (“FN tunneling”). Unlike hot electron and hot hole injection, FN tunneling merely requires applying an electric field between the control gate and source or drain region of the memory cells. Thus, FN tunneling is a faster programming method than hot electron and hot hole injection because it does not require large current to program and/or erase memory cells.
It is therefore desirable to have a non-volatile memory architecture that achieves the benefits of both conventional NAND and NOR architectures, i.e., fast read access times and fast program and erase times.